Title page for ETD etd-11162005-093854

Type of Document Master's Thesis
Author Pulendra, Vanikumari
Author's Email Address vpulen1@lsu.edu
URN etd-11162005-093854
Title Power Supply Current [Ips] Based Testing of CMOS Amplifier Circuit with and without Floating Gate Input Transistors
Degree Master of Science in Electrical Engineering (M.S.E.E.)
Department Electrical & Computer Engineering
Advisory Committee
Advisor Name Title
Ashok Srivastava Committee Chair
Martin Feldman Committee Member
Pratul Ajmera Committee Member
  • operational amplifier
  • analog testing
  • supply current testing
  • floating gate
Date of Defense 2005-08-12
Availability unrestricted
This work presents a case study, which attempts to improve the fault diagnosis and testability of the power supply current based testing methodology applied to a typical two-stage CMOS operational amplifier and is extended to operational amplifier with floating gate input transistors*. The proposed test method takes the advantage of good fault coverage through the use of a simple power supply current measurement based test technique, which only needs an ac input stimulus at the input and no additional circuitry. The faults simulating possible manufacturing defects have been introduced using the fault injection transistors. In the present work, variations of ac ripple in the power supply current IPS, passing through VDD under the application of an ac input stimulus is measured to detect injected faults in the CMOS amplifier. The effect of parametric variation is taken into consideration by setting tolerance limit of 5% on the fault-free IPS value. The fault is identified if the power supply current, IPS falls outside the deviation given by the tolerance limit. This method presented can also be generalized to the test structures of other floating-gate MOS analog and mixed signal integrated circuits.
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