Title page for ETD etd-11142006-103340


Type of Document Dissertation
Author Zhang, Chi
Author's Email Address czhang8@lsu.edu
URN etd-11142006-103340
Title A Study of Phase Noise and Jitter in Submicron CMOS Phase-Locked Loop Circuits
Degree Doctor of Philosophy (Ph.D.)
Department Electrical & Computer Engineering
Advisory Committee
Advisor Name Title
Ashok Srivastava Committee Chair
Guoxiang Gu Committee Member
Martin Feldman Committee Member
Pratul Ajmera Committee Member
Sitharama Iyengar Committee Member
Yitshak Ram Dean's Representative
Keywords
  • VCO
  • PLL
  • phase noise
  • jitter
  • hot carrier
Date of Defense 2006-11-10
Availability unrestricted
Abstract
Phase-locked loops (PLLs) are widely used in communication systems. With the continuously expanding of market for high speed, portable communication devices, low noise CMOS submicron integrated circuit designs of PLL for different applications are in large demand. In this dissertation, phase noise and jitter properties of PLL and its building blocks are investigated both at the physical and system levels.

At the physical level, hot carrier effect in submicron MOSFETs has been considered. As one of the most dominant noise sources of PLL, the voltage-controlled oscillator (VCO) is considered when investigating the noise degradation induced by the hot carrier effect. Experimental results of jitter degradation due to hot carrier effects are presented for different ring oscillator types VCOs designed in 0.5 micron n-well CMOS technology. An increase in RMS jitter by 25% and 10% decrease in oscillation frequency of VCO can be observed after 4 hours hot carrier stress. The hot carrier induced noise degradation on PLL is also presented based on the performance degradation in VCO. Simulation results show 40% decrease in VCO gain after 4 hours stress and a 23% decrease in damping factor and loop bandwidth. Moreover, degradation on PLL noise performance includes a left shift peak in phase noise and a 17% increase in RMS jitter.

At the system level, noise sources in a PLL system are investigated including the input reference noise, VCO noise and the frequency divider noise. Phase noise prediction method for PLL is developed. Experimental phase noise measurement results on 0.5 micron CMOS PLL systems based on different types of VCOs are in close agreement with the predicted phase noise. Therefore, the phase noise prediction method is verified. On the other hand, a 3 GHz adaptive bandwidth PLL based on LC-VCO is designed in 0.25 micron n-well CMOS technology to investigate the phase noise and jitter performance by varying the loop parameters. By considering the noise simulation results based on the adaptive bandwidth feature and the quality factor of the on-chip inductor, PLL loop parameters can be carefully chosen at the design phase to achieve an optimal noise performance.

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