Title page for ETD etd-1113102-222139


Type of Document Master's Thesis
Author Venkata, Harish N
Author's Email Address hvenka1@lsu.edu
URN etd-1113102-222139
Title Ternary and Quaternary Logic to Binary Bit Conversion CMOS Integrated Circuit Design Using Multiple Input Floating Gate MOSFETs
Degree Master of Science in Electrical Engineering (M.S.E.E.)
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Ashok Srivastava Committee Chair
Martin Feldman Committee Member
Pratul Ajmera Committee Member
Keywords
  • floating gate potential diagrams
  • multi-valued logic
  • quaternary logic
  • ternary logic
  • multiple input floating gate MOSFETs
Date of Defense 2002-11-08
Availability unrestricted
Abstract
Multiple-input floating gate MOSFETs and floating gate potential diagrams have been used for conversion of ternary-valued input and quaternary-valued input into corresponding binary-valued output in CMOS integrated circuit design environment. The method is demonstrated through the design of a circuit for conversion of ternary inputs 00 to -1-1 (decimal 0 to -4) and 00 to 11 (decimal 0 to +4) into the corresponding binary bits and for conversion of quaternary inputs (decimal 0 to 3) into the corresponding binary bits (binary 00 to 11) in a standard 1.5 mm digital CMOS technology. The physical design of the circuits is simulated and tested with SPICE using MOSIS BSIM3 model parameters. The conversion method is simple and compatible with the present CMOS process. The circuits could be embedded in digital CMOS VLSI design architectures.

The conversion circuit for ternary inputs into corresponding binary outputs has maximum propagation delay of 8 ns with 0.1 pF simulated capacitive load. The physical layout design occupies an area of 432908 mm2.

The conversion circuit for quaternary inputs to corresponding binary outputs has maximum propagation delay of 6 ns with 0.1 pF simulated capacitive load. The physical layout design occupies an area of 130175 mm2. The conversion circuit achieved significant improvement in the number of devices. A reduction of more than 75% in transistor count was obtained over the previous designs. Measurements of the fabricated devices for the conversion of quaternary input into binary output agree with simulated values.

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