| Type of Document |
Master's Thesis |
| Author |
Mekala, Hemalatha
|
| URN |
etd-11092009-163619 |
| Title |
THIRD ORDER CMOS DECIMATOR DESIGN FOR SIGMA DELTA MODULATORS |
| Degree |
Master of Science (M.S.) |
| Department |
Electrical & Computer Engineering |
| Advisory Committee |
| Advisor Name |
Title |
| Srivastava, Ashok |
Committee Chair |
| Gu, Guoxiang |
Committee Member |
| Wei, Shuangqing |
Committee Member |
|
| Keywords |
- CIC filter
- Decimator
- VLSI
- Hemalatha
|
| Date of Defense |
2009-11-06 |
| Availability |
unrestricted |
Abstract
A third order Cascaded Integrated Comb (CIC) filter has been designed in 0.5μm n-well CMOS process to interface with a second order oversampling sigma-delta ADC modulator. The modulator was designed earlier in 0.5μm technology. The CIC filter is designed to operate with 0 to 5V supply voltages. The modulator is operated with ±2.5V supply voltage and a fixed oversampling ratio of 64. The CIC filter designed includes integrator, differentiator blocks and a dedicated clock divider circuit, which divides the input clock by 64. The CIC filter is designed to work with an ADC that operates at a maximum oversampling clock frequency of up to 25 MHz and with baseband signal bandwidth of up to 800 kHz. The design and performance of the CIC filter fabricated has been discussed.
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| Files |
| Filename |
Size |
Approximate Download Time
(Hours:Minutes:Seconds)
|
| 28.8 Modem |
56K Modem |
ISDN (64 Kb) |
ISDN (128 Kb) |
Higher-speed Access |
| |
MyThesis_9Final.pdf |
4.76 Mb |
00:22:03 |
00:11:20 |
00:09:55 |
00:04:57 |
00:00:25 |
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