Type of Document	Master's Thesis
Author	Srinivasan, Chandra
Author's Email Address	csrini2@lsu.edu
URN	etd-1011103-211310
Title	Arithmetic Logic Unit (ALU) Design Using Reconfigurable CMOS Logic
Degree	Master of Science in Electrical Engineering (M.S.E.E.)
Department	Electrical & Computer Engineering
Advisory Committee	Advisor Name Title Ashok Srivastava Committee Chair Martin Feldman Committee Member Subhash Kak Committee Member
Keywords	multi-input floating gate MOSFET capacitor multivalued logic multiplexer
Date of Defense	2003-09-30
Availability	unrestricted
Abstract Using the reconfigurable logic of multi-input floating gate MOSFETs, a 4-bit ALU has been designed for 3V operation. The ALU can perform four arithmetic and four logical operations. Multi- input floating gate (MIFG) transistors have been promising in realizing increased functionality on a chip. A multi- input floating gate MOS transistor accepts multiple inputs signals, calculates the weighted sum of all input signals and then controls the ON and OFF states of the transistor. This enhances the transistor function to more than just switching. This changes the way a logic function can be realized. Implementing a design using multi-input floating gate MOSFETs brings about reduction in transis tor count and number of interconnections. The advantage of bringing down the number of devices is that a design becomes area efficient and power consumption reduces. There are several applications that stress on smaller chip area and reduced power. Multi- input floating gate devices have their use in memories, analog and digital circuits. In the present work we have shown successful implementation of multi- input floating gate MOSFETs in ALU design. A comparison has been made between adders using different design methods w.r.t transistor count. It is seen that our design, implemented using multi-input floating gate MOSFETs, uses the least number of transistors when compared to other designs. The design was fabricated using double polysilicon standard CMOS process by MOSIS in 1.5mm technology. The experimental waveforms and delay measurements have also been presented.
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