Title page for ETD etd-09282005-014119


Type of Document Master's Thesis
Author Shultz, Evan Ross
Author's Email Address eshult1@lsu.edu
URN etd-09282005-014119
Title High-Frequency CMOS VLSI Chip Testability and on-Chip Interconnect Modeling
Degree Master of Science in Electrical Engineering (M.S.E.E.)
Department Electrical & Computer Engineering
Advisory Committee
Advisor Name Title
Ashok Srivastava Committee Chair
Jin-Woo Choi Committee Member
Martin Feldman Committee Member
Keywords
  • labVIEW
  • time-domain reflectometry (TDR)
  • noise and jitter
  • RLC delay
  • signal integrity
  • field solvers
  • differential ring oscillator
Date of Defense 2005-09-16
Availability unrestricted
Abstract
As high-speed digital and radio-frequency mixed-signal integrated circuits become increasingly common in product designs in industry, it is important for VLSI designers to be familiar with the challenges of chip testing and the behavior of circuit elements, including on-chip interconnect, at high frequencies. Expensive, specialized test equipment and software simulation packages for high-frequency chip testing and design are not always accessible for student research. This thesis documents the setup and characterization of a best-possible environment for high-frequency chip testing and data acquisition using existing laboratory equipment and resources. Experimental methodologies and measurement results of on-chip interconnect signal integrity and delay, ring oscillator noise and timing jitter, and time-domain reflectometry (TDR) testing are presented. Methods of modeling on-chip interconnect at high frequencies using field solvers and equivalent circuits are discussed. Lastly, the designs of single-ended and differential ring oscillators, for use in future voltage-controlled oscillator (VCO) and phase-locked loop (PLL) test chip designs, are presented and analyzed.
Files
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  Shultz_thesis.pdf 2.00 Mb 00:09:15 00:04:45 00:04:09 00:02:04 00:00:10

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