Title page for ETD etd-08262004-170344

Type of Document Master's Thesis
Author Kommana, Syam Prasad SBS
Author's Email Address skomma1@lsu.edu
URN etd-08262004-170344
Title First Order Sigma-Delta Modulator of an Oversampling ADC Design in CMOS Using Floating Gate MOSFETS
Degree Master of Science in Electrical Engineering (M.S.E.E.)
Department Electrical & Computer Engineering
Advisory Committee
Advisor Name Title
Ashok Srivastava Committee Chair
Martin Feldman Committee Member
Subhash Kak Committee Member
  • ADC
  • modulator
  • floating gate MOSFETs
  • oversampling
Date of Defense 2004-05-21
Availability unrestricted
We report a new architecture for a sigma-delta oversampling analog-to-digital converter (ADC) in which the first order modulator is realized using the floating gate MOSFETs at the input stage of an integrator and the comparator. The first order modulator is designed using an 8 MHz sampling clock frequency and implemented in a standard 1.5Ám n-well CMOS process. The decimator is an off-chip sinc-filter and is programmed using the VERILOG and tested with Altera Flex EPF10K70RC240 FPGA board. The ADC gives an 8-bit resolution with a 65 kHz bandwidth.
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