Type of Document Master's Thesis Author Jordan, Matthew Collin Author's Email Address firstname.lastname@example.org URN etd-08192006-134649 Title A Configurable Decoder for Pin-Limited Applications Degree Master of Science (M.S.) Department Electrical & Computer Engineering Advisory Committee
Advisor Name Title Ramachandran Vaidyanathan Committee Chair Jerry Trahan Committee Member Suresh Rai Committee Member Keywords
- pin limitation
- reconfigurable computing
Date of Defense 2006-08-09 Availability unrestricted Abstract
Pin limitation is the restriction imposed on an IC chip by the unavailability of a sufficient number of I/O pins. This impacts the design and performance of the chip, as the amount of information that can be passed through the boundary of the chip becomes limited. One area that would benefit from a reduction of the effect of pin limitation is reconfigurable architectures. In this work, we consider reconfigurable devices called Field Programmable Gate Arrays (FPGAs). Due to pin limitation, current FPGAs use a form of 1-hot decoder to select elements (one frame at a time) during partial reconfiguration. This results in a slow and coarse selection of elements for reconfiguration. We propose a module that performs a focused selection of only those elements that require reconfiguration. This reduces reconfiguration overheads and enables the speeds needed for dynamic reconfiguration.
The problem is that of selecting subsets of an n-element set in a fast, focused and inexpensive manner. This thesis proposes such a configurable decoder that bridges the gap between the inexpensive, but inflexible, fixed 1-hot decoder, and the expensive, but flexible, pure LUT-based decoder. Our configurable decoder uses a LUT with a narrow output and a low cost in tandem with a special fixed decoder called a mapping unit that expands the output of the LUT to a desired n-bit output. We demonstrate several implementations of the mapping unit, each with different capabilities and trade-offs. A key result of this work is that for any gate cost G=O(n logk n) (where k is a constant), if a pure LUT-based solution produces λ independent subsets, then our method produces Ω(λ log n / log log n) independent subsets for the same cost. Our decoder also produces many more dependent subsets (that depend on the choice of the Ω( λ log n / log log n) independent subsets).
We provide simulation results for the configurable decoder and predict future trends from the simulation data; these confirm the theoretical advantages of the proposed decoder. We illustrate the implementation of important subset classes on our configurable decoder and make key observations on a generalized variant.
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