Title page for ETD etd-0712102-103747


Type of Document Dissertation
Author Hong, Jinpyo
URN etd-0712102-103747
Title Memory Optimization Techniques for Embedded Systems
Degree Doctor of Philosophy (Ph.D.)
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Jagannathan Ramanujam Committee Chair
Doris Carver Committee Member
Ramachandran Vaidyanathan Committee Member
Suresh Rai Committee Member
George Cochran Dean's Representative
Keywords
  • compiler optimization
  • memory optimization
  • embedded systems
Date of Defense 2002-07-08
Availability unrestricted
Abstract
Embedded systems have become ubiquitous and as a result optimization of the design and performance of programs that run on these systems have continued to remain as significant challenges to the computer systems research community. This dissertation addresses several key problems in the optimization of programs for embedded systems which include digital signal processors as the core processor.

Chapter 2 develops an efficient and effective algorithm to construct a worm partition graph by finding a longest worm at the moment and maintaining the legality of scheduling. Proper assignment of offsets to variables in embedded DSPs plays a key role in determining the execution time and amount of program memory needed. Chapter 3 proposes a new approach of introducing a weight adjustment function and showed that its experimental results are slightly better and at least as well as the results of the previous works. Our solutions address several problems such as handling fragmented paths resulting from graph-based solutions, dealing with modify registers, and the effective utilization of multiple address registers. In addition to offset assignment, address register allocation is important for embedded DSPs. Chapter 4 develops a lower bound and an algorithm that can eliminate the explicit use of address register instructions in loops with array references.

Scheduling of computations and the associated memory requirement are closely inter-related for loop computations. In Chapter 5, we develop a general framework for studying the trade-off between scheduling and storage requirements in nested loops that access multi-dimensional arrays.

Tiling has long been used to improve the memory performance of loops. Only a sufficient condition for the legality of tiling was known previously. While it was conjectured that the sufficient condition would also become necessary for "large enough" tiles, there had been no precise characterization of what is "large enough." Chapter 6 develops a new framework for characterizing tiling by viewing tiles as points on a lattice. This also leads to the development of conditions under the legality condition for tiling is both necessary and sufficient.

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