Type of Document	Master's Thesis
Author	Ramadass, Balachandran
Author's Email Address	bramad2@lsu.edu
URN	etd-07062009-020543
Title	Processor Design Space Exploration and Performance Prediction
Degree	Master of Science (M.S.)
Department	Electrical & Computer Engineering
Advisory Committee	Advisor Name Title Dr. Lu Peng Committee Chair Dr. Bin Li Committee Co-Chair Dr. J. Ramanujam Committee Member Dr. Jerry Trahan Committee Member
Keywords	Design Space Exploration Performance Prediction MART-Aided Models
Date of Defense	2009-04-16
Availability	unrestricted
Abstract The use of simulation is well established in processor design research to evaluate architectural design trade-offs. More importantly, Cycle by Cycle accurate simulation is widely used to evaluate the new designs in processor research because of its accurate and detailed processor performance measurement. However, only configuration in a subspace can be simulated in practice due to its long simulation time and limited resources, leading to suboptimal conclusions that might not be applied to the larger design space. In this thesis, we propose a performance prediction approach which employs a state-of-the-art technique from experimental design, machine learning and data mining. Our model can be trained initially by using Cycle by Cycle accurate simulation results, and then it can be implemented to predict the processor performance of the entire design space. According to our experiments, our model predicts the performance of a single-core processor with median percentage error ranging from 0.32% to 3.01% for about 15 million design spaces by using only 5000 initial independently sampled design points as a training set. In CMP the median percentage error ranges from 0.50% to 1.47% for about 9.7 million design spaces by using only 5000 independently sampled CMP design points as a training set. Apart from this, the model also provides quantitative interpretation tools such as variable importance and partial dependence of the design parameters.
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