Title page for ETD etd-06292006-011812


Type of Document Master's Thesis
Author Golla, Kalyan Madhav
Author's Email Address kgolla2@lsu.edu
URN etd-06292006-011812
Title ∆IDDQ Testing of a CMOS 12-Bit Charge Scaling Digital-to-Analog Converter
Degree Master of Science in Electrical Engineering (M.S.E.E.)
Department Electrical & Computer Engineering
Advisory Committee
Advisor Name Title
Ashok Srivastava Committee Chair
Jin-Woo Choi Committee Member
Suresh Rai Committee Member
Keywords
  • iddq testing
  • cmos dac
  • fit
  • charge scaling
Date of Defense 2006-05-02
Availability unrestricted
Abstract
This work presents design, implementation and test of a built-in current sensor (BICS) for ∆IDDQ testing of a CMOS 12-bit charge scaling digital-to-analog converter (DAC). The sensor uses power discharge method for the fault detection. The sensor operates in two modes, the test mode and the normal mode. In the test mode, the BICS is connected to the circuit under test (CUT) which is DAC and detects abnormal currents caused by manufacturing defects. In the normal mode, BICS is isolated from the CUT. The BICS is integrated with the DAC and is implemented in a 0.5 μm n-well CMOS technology. The DAC uses charge scaling method for the design and a low voltage (0 to 2.5 V) folded cascode op-amp. The built-in current sensor (BICS) has a resolution of 0.5 μA. Faults have been introduced into DAC using fault injection transistors (FITs). The method of ∆IDDQ testing has been verified both from simulation and experimental measurements.
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