| Type of Document |
Master's Thesis |
| Author |
Chamakura, Anand K
|
| Author's Email Address |
achama1@lsu.edu |
| URN |
etd-05272004-162258 |
| Title |
IDDQ Testing of a CMOS First Order Sigma-Delta Modulator of an 8-Bit Oversampling ADC |
| Degree |
Master of Science (M.S.) |
| Department |
Electrical & Computer Engineering |
| Advisory Committee |
| Advisor Name |
Title |
| Ashok Srivastava |
Committee Chair |
| Martin Feldman |
Committee Member |
| Suresh Rai |
Committee Member |
|
| Keywords |
- iddq
- adc
- sigma delta modulator
|
| Date of Defense |
2004-04-13 |
| Availability |
unrestricted |
Abstract
This work presents IDDQ testing of a CMOS first order sigma-delta modulator of an 8-bit oversampling analog-to-digital converter using a built-in current sensor [BICS]. Gate-drain, source-drain, gate-source and gate-substrate bridging faults are injected using fault injection transistors. All the four faults cause varying fault currents and are successfully detected by the BICS at a good operation speed. The BICS have a negligible impact on the performance of the modulator and an external pin is provided to completely cut-off the BICS from the modulator. The modulator was designed and fabricated in 1.5 μm n-well CMOS process. The decimator was designed on Altera's FLEXE20K board using Verilog. The modulator and decimator were assembled together to form a sigma-delta ADC.
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| Filename |
Size |
Approximate Download Time
(Hours:Minutes:Seconds)
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56K Modem |
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Chamakura_thesis.pdf |
2.17 Mb |
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