Title page for ETD etd-04282011-065004


Type of Document Master's Thesis
Author Kongari, Raghavendra
Author's Email Address rkonga1@tigers.lsu.edu
URN etd-04282011-065004
Title Cost and Performance Modeling of the MU-Decoder
Degree Master of Science in Electrical Engineering (M.S.E.E.)
Department Electrical & Computer Engineering
Advisory Committee
Advisor Name Title
Vaidyanathan, Ramachandran Committee Chair
Gunturk, Bahadir K. Committee Member
Skavantzos, Alexander Committee Member
Keywords
  • fpga
  • subset generation
  • reconfigurable computing
  • configurable decoder
Date of Defense 2011-04-26
Availability unrestricted
Abstract
In this thesis we study the implementation details of the MU-Decoders, a recently proposed hardware module that has been theoretically shown to be superior to other methods for generating subsets of large sets. Our study confirms this advantage.

Specifically, we compare the performance of implementations of the LUT-Decoder (the most common configurable decoder) to the MU-Decoder. We show that for while the LUT-Decoder is slightly better than the MU-Decoder for arbitrary (and artificial) inputs, for a large class of inputs called totally ordered subsets, that have practical significance, the MU-Decoder is vastly superior in area to the LUT-Decoder. In terms of delay and power too, the MU-Decoder performs better than the LUT-Decoder.

This work is based on a series of time-optimized and area-optimized implementations of key building blocks of the MU-Decoder that help construct models for both the LUT-Decoder and the MU-Decoder. These models serve to predict the delay, area and power of these decoders at sizes that may not be practical to implement in an academic setting.

As a part of the work, multiplexers, one-hot decoders, multicast hard-wiring, and memory modules are implemented and modeled. These are all commonly used elements of digital systems. Therefore this work may also be of independent interest, beyond MU-Decoders.

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