Type of Document	Master's Thesis
Author	Anantha, Raghavendra Reddy
Author's Email Address	ranant1@lsu.edu
URN	etd-04142005-184453
Title	A Programmable CMOS Decimator for Sigma-Delta Analog-to-Digital Converter and Charge Pump Circuits
Degree	Master of Science in Electrical Engineering (M.S.E.E.)
Department	Electrical & Computer Engineering
Advisory Committee	Advisor Name Title Ashok Srivastava Committee Chair Martin Feldman Committee Member Pratul Ajmera Committee Member
Keywords	clock divider circuit cmos decimator charge pump dc-dc converter clock booster circuit cic filter
Date of Defense	2005-04-08
Availability	unrestricted
Abstract PROGRAMMABLE DECIMATOR FOR SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTER: In this work a programmable decimator design has been presented in 1.5 μm n-well CMOS process for integration with an existing modulator to form a sigma-delta analog-to-digital converter (ADC). The decimator is implemented using a second order Cascaded Integrator Comb (CIC) filter and can be programmed to work with two different oversampling ratios of 64 and 16. The input to the decimator is provided from a first order modulator. With oversampling ratios of 64 and 16, an output resolution of 10-bit and 7-bit, respectively are achieved for the ADC. The ADC can be operated with an oversampling clock frequency of up to 8 MHz and with an input signal bandwidth of up to 65 KHz. An in-built clock divider circuit has been designed which generates two output clocks whose frequencies are equal to the input clock frequency divided by the oversampling ratios 64 and 16. CHARGE PUMP CIRCUITS: The charge pump CMOS circuits are presented which are designed based on a new technique of internal clock voltage boosting. Four and six-stage charge pumps are implemented in 1.5 μm n-well CMOS process. The charge pump circuits can be operated in 1.2 V - 3 V power supply voltage range. Outputs of 12.5 V and 17.8 V are measured from four and six-stage charge pumps, respectively with a 3 V power supply. The charge pump circuits can also be used to generate clock voltages higher than the input clock voltage. In the present design, clock voltages of 8 V and 11 V have been generated from four-stage and six-stage charge pumps, respectively which are nearly 2.5 and 4 times the input clock voltage of 3 V. The technique of boosting the clock internally has been applied in implementation of a revised version of battery powered Bio-implantable Electrical Stimulation System (BESS) integrated circuit.
Files	Filename       Size       Approximate Download Time (Hours:Minutes:Seconds)     28.8 Modem   56K Modem   ISDN (64 Kb)   ISDN (128 Kb)   Higher-speed Access    Anantha_thesis.pdf 5.58 Mb 00:25:50 00:13:17 00:11:37 00:05:48 00:00:29

If you have questions or technical problems, please Contact LSU-ETD Support.