Title page for ETD etd-0414102-135429

Type of Document Master's Thesis
Author Neoh, Cheowway
Author's Email Address cneoh1@lsu.edu
URN etd-0414102-135429
Title Computing Moments of a Binary Horizontally/Vertically Convex Image Using Run-Time Reconfiguration
Degree Master of Science in Electrical Engineering (M.S.E.E.)
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Jerry Trahan Committee Chair
Ramachandran Vaidyanathan Committee Member
Suresh Rai Committee Member
  • moments
  • run-time reconfiguration
  • convex images
Date of Defense 2002-03-27
Availability unrestricted
In this thesis, we present a design for computing moments of a binary horizontally/vertically convex image on an FPGA chip, using run-time reconfiguration. We compute the moments of up to third order for a total of 16 moments. We address how run-time reconfiguration speeds up moment computations without taking up huge hardware resources. Since we are considering a binary horizontally/vertically convex image, we look at an alternative method in moment computations that utilizes constant coefficient multipliers. We divide the image into segments and process one segment at a time. We reconfigure the constant coefficient multipliers before processing the next segment. This thesis also looks at the interactions between different logic units for moment computations. We provide an estimate of the total number of CLBs used to implement this design on an FPGA chip. Finally, we address variations of this particular type of image, such as non-binary and non-convex and determine whether this design is still applicable in those instances.
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