Type of Document Master's Thesis Author Ashrafi, Arash Author's Email Address firstname.lastname@example.org, email@example.com URN etd-04112016-050653 Title An Architecture for Configuring an Efficient Scan Path for a Subset of Elements Degree Master of Science in Electrical Engineering (M.S.E.E.) Department Electrical & Computer Engineering Advisory Committee
Advisor Name Title Vaidyanathan, Ramachandran Committee Chair Koppelman, David Committee Member Trahan, Jerry Committee Member Keywords
- partial reconfiguration
- scan path
- configuration bitstream
Date of Defense 2016-04-07 Availability unrestricted Abstract
LaTeX4Web 1.4 OUTPUT
Field Programmable Gate Arrays (FPGAs) have many modern applications. A feature of FPGAs is that they can be reconfigured to suit the computation. One such form of reconfiguration, called partial reconfiguration (PR), allows part of the chip to be altered. The smallest part that can be reconfigured is called a frame. To reconfigure a frame, a fixed number of configuration bits are input (typically from outside) to the frame.
Thus PR involves (a) selecting a subset C Í S of k out of n frames to configure and (b) inputting the configuration bits for these k frames. The, recently proposed, MU-Decoder has made it possible to select the subset C quickly. This thesis involves mechanisms to input the configuration bits to the selected frames.
Specifically, we propose a class of architectures that, for any subset C Í S (set of frames), constructs a path connecting only the k frames of C through which the configuration bits can be scanned in. We introduce a Basic Network that runs in Q (k log n) time, where k is the number of frames selected out of the total number n of available frames; we assume the number of configuration bits per frame is constant. The Basic Network does not exploit any locality or other structure in the subset of frames selected. We show that for certain structures (such as frames that are relatively close to each other) the speed of reconfiguration can be improved. We introduce an addition to the Basic Network that suggests the fastest clock speed that can be employed for a given set of frames. This enhancement decreases configuration time to O(k log k) for certain cases. We then introduce a second enhancement, called shortcuts, that for certain cases reduces the time to an optimal O(k). All the proposed architectures require an optimal Q(n) number of gates.
We implement our networks on the CAD tools and show that the theoretical predictions are a good reflection of the network¢s performance.
Our work, although directed to FPGAs, may also apply to other applications; for example hardware testing and novel memory accesses.
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