Title page for ETD etd-04012006-004043


Type of Document Dissertation
Author Jiang, Li
URN etd-04012006-004043
Title Integrated Circuit Metrology by Multilevel Patterning Technology
Degree Doctor of Philosophy (Ph.D.)
Department Electrical & Computer Engineering
Advisory Committee
Advisor Name Title
Martin Feldman Committee Chair
Ashok Srivastava Committee Member
Pratul K. Ajmera Committee Member
Steven G. Hall Committee Member
Theda Daniels-Race Committee Member
Joseph A. Giaime Dean's Representative
Keywords
  • overlay
  • metrology
  • image placement
  • coordinate tool
  • encoder
  • integrated circuit
Date of Defense 2006-03-16
Availability unrestricted
Abstract
A low cost, high accuracy method is described in detail for measuring image placement in integrated circuit manufacture. The method measures both the overlay between levels and the absolute placement of features in a single level. The overlay is measured by a technique which views multiple levels separately. The absolute distances between features on a test wafer are measured by comparing the features to precision gratings. Optical imaging techniques are described for viewing and analyzing the grating images, as well as for measuring distortions in the observing microscope and a video camera. These techniques permit image placement measurements to be made to an accuracy limited by that of available gratings, at present about 2 nm. In addition they were applied to a prototype encoder system, demonstrating the potential improvement in commercial encoders by a factor of more than 100.
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