Type of Document Master's Thesis Author Tatineni, Shobharani Author's Email Address firstname.lastname@example.org URN etd-0114102-153450 Title Dynamic Scheduling, Allocation, and Compaction Scheme for Real-Time Tasks on FPGAs Degree Master of Science in Electrical Engineering (M.S.E.E.) Department Electrical and Computer Engineering Advisory Committee
Advisor Name Title Jerry L. Trahan Committee Chair Jaquannathan Ramanujam Committee Member Ramachandran Vaidyanathan Committee Member Suresh Rai Committee Member Keywords
- hardware reconfiguration
Date of Defense 2001-12-19 Availability unrestricted AbstractRun-time reconfiguration (RTR) is a method of computing on reconfigurable logic,
typically FPGAs, changing hardware configurations from phase to phase of a
computation at run-time. Recent research has expanded from a focus on a single
application at a time to encompass a view of the reconfigurable logic as a resource
shared among multiple applications or users.
In real-time system design, task deadlines play an important role. Real-time
multi-tasking systems not only need to support sharing of the resources in space, but
also need to guarantee execution of the tasks. At the operating system level, sharing
logic gates, wires, and I/O pins among multiple tasks needs to be managed. From the
high level standpoint, access to the resources needs to be scheduled according to task
This thesis describes a task allocator for scheduling, placing, and compacting
tasks on a shared FPGA under real-time constraints. Our consideration of task
deadlines is novel in the setting of handling multiple simultaneous tasks in RTR.
Software simulations have been conducted to evaluate the performance of the
proposed scheme. The results indicate significant improvement by decreasing the
number of tasks rejected.
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